Hardware interview practice
Reorder an eight-packet sequence window
A chiplet receiver accepts eight-bit sequence numbers out of order and emits them in order. Its receive window contains the next eight sequence values modulo 256. Implement the SystemVerilog reorder window with duplicate and range checks.
Starting point
Question code
input logic clk,rst_n,in_valid; output logic in_ready;
input logic [7:0] in_seq; input logic [31:0] in_data;
output logic out_valid; input logic out_ready;
output logic [7:0] out_seq; output logic [31:0] out_data;
output logic error;Reviewed example
Work through one case
Input
Starting at expected_seq=0 with out_ready=1, packets arrive in sequence-number order 2/data22, 0/data0, then 1/data11.Expected output
Accepted outputs are 0/data0, 1/data11, and 2/data22 in that order with error=0.Sequence 2 waits in its distance-two slot until the missing zero and one packets arrive and successive pops close the gap.
What to cover
Requirements
- During reset drive in_ready=0, out_valid=0, out_seq=0, and out_data=0; after reset expected_seq=0, all slots and error are clear, and classify input by unsigned eight-bit in_seq-expected_seq.
- in_ready is always one outside reset. On an input handshake, store a distance 0..7 only if that slot is empty; otherwise drop it and set sticky error.
- out_valid is slot-zero occupancy. When invalid drive out_seq=out_data=0; when valid, hold expected_seq and its data stable while out_ready=0.
- On output handshake, shift and increment expected_seq. A simultaneous distance-0 input is a duplicate of retiring slot zero and is dropped with error; an accepted distance 1..7 input lands after the shift at slot distance-1.