Hardware interview practice

Reject Input Glitches Shorter than Four Samples

MediumRTL DesignSystemVerilog

An asynchronous control input may glitch. A 100 MHz destination must first synchronize it and then change its filtered output only after seeing the opposite level on four consecutive destination samples. Implement the synchronizer and four-sample stability filter.

Starting point

Question code

module stable4_filter(
 input logic clk,rst_n,async_in,
 output logic filtered_out
);

Reviewed example

Work through one case

Input

Case 1: From filtered_out=0, synchronized samples 1,1,1,0
Case 2: Scenario: From filtered_out=0, synchronized samples 1,1,1,1 change the output to 1 on the fourth sample.
Case 3: Scenario: From filtered_out=1, four consecutive synchronized zeros change the output to 0 by the same rule.

Expected output

Case 1: Leave the output at 0 and clear progress.
Case 2: Expected behavior: From filtered_out=0, synchronized samples 1,1,1,1 change the output to 1 on the fourth sample.
Case 3: Expected behavior: From filtered_out=1, four consecutive synchronized zeros change the output to 0 by the same rule.

The shown result follows by applying this rule: The CDC synchronizer is separate from the four-sample qualification state. The cases also demonstrate this requirement: A return to the current output before four differing samples restarts qualification; use a saturating or explicitly cleared counter so it cannot wrap into a false transition.

What to cover

Requirements

Use a two-flop destination-clock synchronizer for async_in, mark or preserve it as a synchronizer, and feed the filter only from its second stage.
Active-low synchronous reset clears both synchronizer stages, filtered_out, and the differing-sample counter.
When the synchronized sample equals filtered_out, clear the counter; otherwise count consecutive differing samples, update filtered_out on the fourth such sample, and clear the counter.
A return to the current output before four differing samples restarts qualification; use a saturating or explicitly cleared counter so it cannot wrap into a false transition.