Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Recognize LL/SC reservation failure

Hardware interview practice

Recognize LL/SC reservation failure

EasyComputer ArchitectureSystemVerilog

When should store-conditional fail in a load-linked/store-conditional implementation?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. When an architecture-defined event, such as a conflicting coherent write, invalidates the reservation before SC.
  2. B. Whenever the store data equals the old value.
  3. C. Only when the cache line is clean.
  4. D. Never; SC always performs the store.
asic.fyi · Learn silicon end to end.info@asic.fyi