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Hardware interview practice

Randomize weighted onehot-or-zero requests

MediumConstraintsSystemVerilog

Randomize an 8-bit request that is onehot 80% of the time and all zero 20% of the time, with an index naming the active bit.

Reviewed example

Work through one case

Input
randomize active with 80:20 active/inactive weighting, 8-bit req, and 3-bit idx
Expected output
One valid active result: idx=5, req=8'b0010_0000

Exactly req[5] is asserted. The inactive result req=0,idx=0 and seven other active indices remain valid, so one solve is non-unique.

What to cover

Requirements

  1. When active, exactly one request bit must be set.
  2. When inactive, both req and idx must be zero.
  3. When active, req[idx] must be the asserted bit.