Skip to question
ASIC.FYI
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
ASIC.FYI/Interview questions/Predict a strict round-robin grant

Q292·Free·SystemVerilog

Predict a strict round-robin grant

Difficulty
Medium
Topic
Arbiters
Language
SV
Interview prompt

Question

Build a stateful predictor for an N-port strict round-robin arbiter. Given a request vector, return the winning port, return -1 when idle, and move priority to the port immediately after each accepted winner.

Strict round-robin predictor interface with request vector, next-start pointer, accepted handshake, and winner output
The pointer identifies where the circular scan begins and advances only after an accepted winner.
Starting point

Question code

class RRPredictor #(int N = 8);
  function int predict_next(bit [N-1:0] reqs);
  function void update_state(int grant_idx);
  function void reset();
endclass
Reviewed example

Trace one case

Input
N=4,next_priority=0; active request ports={1,3}; predict twice
Expected output
grant port1 then port3; next_priority returns to0

The strict circular scan begins at the saved pointer and moves priority to the port immediately after each accepted winner.

What to cover

Requirements

  1. Give port zero first priority after reset.
  2. Search circularly from the current next-priority port.
  3. Return one winning index or -1 when no request is active.
  4. Update state only for a valid grant index.
  5. Preserve fairness for continuously asserted requesters.
Exact question handoffPractice Q292

Solve it in the question bank, keep your progress, and reveal the reviewed solution when your access allows.

Open in question bank →
Solution accessA Free account unlocks the complete reviewed solution.
Continue learning

SystemVerilog

  • Arbiters
  • Round robin
  • Circular priority
Interview preparation guide →
Continue practicing

Related questions

Q293 · ArbitersSelect round-robin winners with rotate and isolate→Q216 · ArbitersPredict weighted round-robin grants→Q182 · ArbitersDetect a starving arbiter requester→
ASIC.FYI · Learn silicon end to end.info@asic.fyi