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Hardware interview practice

Packed and unpacked array meaning

EasySystemVerilogSystemVerilog

A testbench API requires an unpacked array of four elements. Each element is one packed 8-bit logic vector. Which declaration has exactly that shape?

Choose one

Answer choices

  1. A. logic [7:0] data [0:3];
  2. B. logic [0:3][7:0] data;
  3. C. logic data [7:0][0:3];
  4. D. logic [31:0] data;