Hardware interview practice
Order the FPGA Build and Bring-Up Flow
A new RTL block will be verified, implemented in an FPGA, loaded onto a board, and debugged on hardware. Which ordering is the best baseline flow?
Choose one
Answer choices
- A. Write RTL and constraints; lint and run simulation/formal checks; synthesize; place, route, and run timing analysis; generate the bitstream; program the FPGA; then use on-board tests and embedded logic analyzers for hardware-only issues.
- B. Generate a bitstream directly from the testbench, program it, and synthesize only if the hardware test fails.
- C. Synthesize before writing timing or pin constraints, then treat a successful programming operation as proof that timing closed.
- D. Run place-and-route first, simulate the routed design before RTL exists, and use lint only after board bring-up.