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Hardware interview practice

Order common UVM phases

EasyUVMSystemVerilog

A component creates children, connects TLM ports, runs timed stimulus, and checks final results. Which phase order is correct?

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Answer choices

  1. A. connect_phase, build_phase, check_phase, run_phase.
  2. B. build_phase, run_phase, connect_phase, check_phase.
  3. C. build_phase, connect_phase, run_phase, check_phase.
  4. D. run_phase, build_phase, connect_phase, check_phase.
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