Hardware interview practice

Implement a Three-Tap FIR from Its Transfer Function

MediumComputer ArchitectureSystemVerilog

The supplied transfer function is `H(z)=1+2z^-1+z^-2`. Signed 16-bit samples arrive with a valid pulse. Delay elements advance only on accepted valid samples. Full-precision signed 18-bit output is sufficient because the coefficient absolute sum is four. Design the direct-form FIR RTL and verify its difference equation, history, gaps, reset, and one-cycle output latency.

Starting point

Question code

module fir3(input logic clk,rst_n,in_valid,
 input logic signed [15:0] x,
 output logic out_valid, output logic signed [17:0] y);
// y[n]=x[n]+2*x[n-1]+x[n-2]
// accept at E0; output is visible just after the following edge E1

Reviewed example

Work through one case

Input

Case 1: Accept [1,2,3] on E0,E1,E2
Case 2: Accept impulse [5,0,0] on consecutive edges
Case 3: Accept 7, wait three invalid cycles, then accept 1

Expected output

Case 1: outputs [1,4,8] just after E1,E2,E3 respectively.
Case 2: outputs [5,10,5], each one edge after its input.
Case 3: output 7 one edge after its acceptance and output 15 one edge after the later acceptance; invalid gaps do not insert zero samples.

The shown result follows by applying this rule: The implementation exactly realizes the stated difference equation with two accepted-sample delays. The cases also demonstrate this requirement: Reset clears history and valid state. No saturation or rounding is used; all signed extensions and the multiply-by-two shift must preserve sign.

What to cover

Requirements

Maintain two signed 16-bit history registers initialized to zero. Shift history only when `in_valid` is sampled high.
At an accepting edge E0, compute the signed full-precision equation from the new sample and the pre-E0 history, capture it in an 18-bit pending-result register, capture pending-valid, and then update the two history registers.
At the following edge E1, transfer the pending result and valid bit to the output registers. Thus an item accepted at E0 is visible just after E1; back-to-back inputs still produce one ordered result per edge after fill, while invalid gaps hold history and create no output transaction.
Reset clears history and valid state. No saturation or rounding is used; all signed extensions and the multiply-by-two shift must preserve sign.