Hardware interview practice

Implement a Safe Integer Clock-Enable Divider

MediumTimingSystemVerilog

A block needs an enable pulse every N source-clock cycles for both even and odd N. To avoid creating an unconstrained fabric clock, the released implementation produces a one-cycle clock enable rather than driving a new clock net. Implement a parameterized divider for `N>=2` and derive the tick positions for even N=4 and odd N=5.

Starting point

Question code

module int_div_ce #(parameter int N=5)(input logic clk,rst_n,en,
 output logic tick);
// tick is a one-clk pulse; count advances only while en=1
// reset restarts the interval; N must be at least 2

Reviewed example

Work through one case

Input

Case 1: Set N=4 and hold en high continuously
Case 2: Set N=5 and hold en high continuously
Case 3: Set N=4; after two enabled edges, hold en low for three cycles, then enable two more edges

Expected output

Case 1: tick is high on enabled edges 4,8,12,...
Case 2: tick is high on enabled edges 5,10,15,...
Case 3: the second later enabled edge produces the first tick; disabled cycles do not count

The shown result follows by applying this rule: The counter and comparison handle both even and odd N without an off-by-one error. The cases also demonstrate this requirement: State that an exact 50%-duty odd-divided clock needs both-edge or dedicated clock-generation resources; do not use this enable pulse as a combinationally gated clock.

What to cover

Requirements

Use a counter wide enough for 0 through N-1. Reset clears the counter and tick; `en=0` holds the counter and forces tick low.
On each enabled edge, pulse tick when the old count is N-1 and reload zero; otherwise increment and keep tick low.
The first tick after reset occurs on the Nth enabled rising edge, independent of disabled gaps. Subsequent ticks are exactly N enabled edges apart.
State that an exact 50%-duty odd-divided clock needs both-edge or dedicated clock-generation resources; do not use this enable pulse as a combinationally gated clock.