Hardware interview practice
Identify VCS Build and Simulation Artifacts
A SystemVerilog/UVM regression uses Synopsys VCS with separate build and run steps. Which workflow description is correct?
Choose one
Answer choices
- A. `csrc` is the only required user source directory, so deleting the original SystemVerilog files never affects a rebuild.
- B. `simv` is the synthesized gate-level netlist, and running it programs the design into an FPGA.
- C. Compilation executes all test sequences immediately, while elaboration occurs after the simulation log has been written.
- D. VCS compiles sources and elaborates the chosen top into a simulation executable, commonly `simv`; build support may appear in `simv.daidir` and `csrc`, while running `simv` creates runtime logs and requested wave or coverage data. Exact names depend on options and version.