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Generate a Divide-by-2.5 Fractional Tick Sequence

HardTimingSystemVerilog

A scheduling block needs a one-source-cycle enable pulse at an average divide ratio of 2.5. It may alternate integer intervals of two and three enabled source cycles. This is an enable sequence, not a clock-tree output. Implement the alternating-period divider and quantify its average frequency and deterministic timing error.

Starting point

Question code

module div2p5_tick(input logic clk,rst_n,en, output logic tick);
// interval sequence after reset: 2,3,2,3,... enabled edges
// tick width: one clk cycle; en=0 freezes interval state and counter
// first tick occurs on enabled edge 2
Reviewed example

Work through one case

Input
Case 1: Hold en high continuously
Case 2: Observe the first four tick intervals
Case 3: After enabled edge 3, hold en low for four source-clock cycles, then resume enabled edges
Expected output
Case 1: tick occurs on enabled edges 2,5,7,10,12,15,...
Case 2: the intervals are 2,3,2,3 edges; their average is (2+3+2+3)/4 = 2.5
Case 3: the next tick remains due on the second later enabled edge, enabled edge 5 of the sequence

The shown result follows by applying this rule: The state machine produces the exact 2,3 alternating interval sequence and one-cycle tick pulses. The cases also demonstrate this requirement: Relative to ideal uniformly spaced 2.5-edge events, actual intervals are -0.5 and +0.5 source cycles; report this deterministic period jitter and do not claim a stable 50% clock duty cycle.

What to cover

Requirements

  1. Reset selects a two-edge first interval, clears the interval counter, and clears tick. Disabled cycles freeze the counter and 2/3 selector and force tick low.
  2. Pulse on the last enabled edge of the current interval, reload the counter, and alternate the next interval between three and two enabled edges.
  3. Over every pair of intervals, exactly two ticks occur in five enabled edges, so the long-term tick rate is `fclk/2.5`.
  4. Relative to ideal uniformly spaced 2.5-edge events, actual intervals are -0.5 and +0.5 source cycles; report this deterministic period jitter and do not claim a stable 50% clock duty cycle.