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Hardware interview practice

Find vectors that expose internal stuck-at faults

MediumFormal VerificationSystemVerilog

For n1 = a & b and y = n1 | c, give one input vector that detects n1 stuck-at-0 and one that detects n1 stuck-at-1. Show both good and faulty outputs.

Reviewed example

Work through one case

Input
SA0 test (1,1,0); SA1 test (0,0,0)
Expected output
SA0: good y=1, faulty y=0. SA1: good y=0, faulty y=1.

Each vector first forces the good internal node opposite the stuck value, then uses the OR gate's non-controlling input c=0 to expose the difference.

What to cover

Requirements

  1. Use vector order (a,b,c) and analyze one fault at a time.
  2. Sensitize stuck-at-0 by making fault-free n1=1, and stuck-at-1 by making fault-free n1=0.
  3. Set c=0 so the internal difference propagates through the OR gate to y.
  4. Call a vector detecting only when good y and faulty y differ, and explain why c=1 masks both faults.