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Hardware interview practice

Distinguish a latch from a flip-flop

EasyRTL DesignSystemVerilog

Block A uses `always_latch if (en) q_a <= d;`. Block B uses `always_ff @(posedge clk) q_b <= d;`. Which statement correctly describes the storage behavior?

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Answer choices

  1. A. A samples only when en falls, while B remains transparent for the entire high phase of clk.
  2. B. A is level-sensitive and can follow d while en is active; B samples d only at the rising clock edge.
  3. C. Both blocks are edge-triggered because nonblocking assignment is used in each block.
  4. D. A is combinational because it has no explicit clock, while B is the only block that stores state.
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