Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Detect a linked-list cycle

Hardware interview practice

Detect a linked-list cycle

EasyLinked ListsSystemVerilog

Return 1 when a singly linked list contains a cycle and 0 when it terminates at null.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Reviewed example

Work through one case

Input
1 -> 2 -> 3, with node 3.next pointing back to node 2
Expected output
1 (cycle present)

The slow and fast pointers eventually meet inside the 2 -> 3 loop without modifying the list.

What to cover

Requirements

  1. Use constant extra space.
  2. Handle empty and one-node lists safely.
  3. Do not modify list links.
Continue practicing

Related questions

Linked ListsFind the middle node→Linked ListsReverse a singly linked list→Linked ListsMerge two sorted linked lists→
asic.fyi · Learn silicon end to end.info@asic.fyi