Hardware interview practice

Design and verify a round-robin arbiter

HardRTL DesignSystemVerilog

Design a four-request round-robin arbiter with one-cycle one-hot grants and verification for safety and bounded fairness.

Starting point

Question code

input logic clk, rst_n;
input logic [3:0] req;
output logic [3:0] gnt;

Reviewed example

Input

Last grant was requester 1; req[1] and req[3] remain high

Expected output

Next grant is requester 3; the following successful arbitration grants requester 1

Scanning starts at 2 after grant 1, so requester 3 is encountered before requester 1.

What to cover

Grant at most one asserted request.
After granting i, begin the next scan at i+1 modulo four.
When no request is active, grant zero and preserve the priority pointer.
Prove a continuously asserted request is served within four successful arbitration cycles.

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