Hardware interview practice

Convert a Turnstile Protocol into an FSM

MediumProtocols and InterfacesSystemVerilog

A turnstile starts LOCKED. A coin while LOCKED moves to UNLOCKED and pulses `unlock`. A push while UNLOCKED permits one passage, returns to LOCKED, and pulses `pass`. A push while LOCKED pulses `alarm`; a coin while UNLOCKED pulses `refund`. Coin and push high together are invalid and leave state unchanged while pulsing `alarm`. Design the state-transition diagram and implement the complete synchronous Moore-state/Mealy-pulse controller.

Starting point

Question code

module turnstile(input logic clk,rst_n,coin,push,
 output logic locked,unlock,pass,refund,alarm);
// coin/push are synchronous one-cycle events
// pulse outputs are one cycle; reset state is LOCKED

Reviewed example

Work through one case

Input

Case 1: LOCKED + coin
Case 2: UNLOCKED + push
Case 3: Either state + coin=1,push=1

Expected output

Case 1: UNLOCKED, unlock=1, locked=0 on the updated state, all other pulses 0.
Case 2: LOCKED, pass=1, refund=alarm=unlock=0.
Case 3: state unchanged and alarm=1 only.

The shown result follows by applying this rule: The diagram and RTL implement all state/event combinations including simultaneous invalid inputs. The cases also demonstrate this requirement: Default every pulse low each cycle, define no-event as state hold, and include illegal-state recovery to LOCKED with no transaction pulse.

What to cover

Requirements

Use exactly two stored states, LOCKED and UNLOCKED; active-low reset enters LOCKED and clears all pulse outputs.
Implement the four single-event transitions exactly as stated and drive `locked` directly from registered state.
When coin and push are both high, keep the old state, pulse alarm only, and do not pulse unlock, pass, or refund.
Default every pulse low each cycle, define no-event as state hold, and include illegal-state recovery to LOCKED with no transaction pulse.