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Hardware interview practice

Convert a synchronous level into a one-cycle rising pulse

EasyRTL DesignSystemVerilog

The input level is already synchronous to clk and may remain high for any number of cycles. Implement the rising-edge pulse detector.

Starting point

Question code

module rise_pulse(
  input logic clk,rst_n,level,
  output logic pulse
);
Reviewed example

Work through one case

Input
Case 1: Sample levels 0,1,1,1
Case 2: After an initial synchronized low, sample levels 1,0,1
Case 3: Reset, then sample level=0
Expected output
Case 1: pulse is 0,1,0,0
Case 2: pulse is 1,0,1
Case 3: pulse and the delayed level remain 0

The shown result follows by applying this rule: Register the previous level and compute pulse from current level AND NOT previous level on each edge. The cases also demonstrate this requirement: A falling edge produces no pulse; a later low-to-high transition may produce a new pulse.

What to cover

Requirements

  1. An active-low synchronous reset clears the delayed level and pulse.
  2. Pulse for exactly one cycle when level is one and its previous sampled value was zero.
  3. A level held high for multiple cycles produces no pulse after the first high cycle.
  4. A falling edge produces no pulse; a later low-to-high transition may produce a new pulse.