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Hardware interview practice

Constrain a size-aligned address

EasyConstraintsSystemVerilog

Randomize an address in 0x8000_0000 through 0x8000_FFFF with transfer size 1, 2, 4, or 8, aligned to that size.

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Reviewed example

Work through one case

Input
randomize size from {1,2,4,8} and address in 0x8000_0000..0x8000_FFFF
Expected output
One valid result: size=8, address=0x8000_0040

The transfer size is legal, the address is inside the aperture, and 0x8000_0040 modulo 8 is zero. Other aligned pairs are valid.

What to cover

Requirements

  1. Choose only legal power-of-two transfer sizes.
  2. Keep the address inside the inclusive aperture.
  3. Require addr modulo size to equal zero.
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