Hardware interview practice
Constrain a nonzero 32-bit power of two
Write a solver-friendly SystemVerilog constraint for a 32-bit randomized field that contains exactly one set bit and therefore represents a nonzero power of two.
Starting point
Question code
class one_hot_value;
rand bit [31:0] value;
endclassReviewed example
Work through one case
Input
value=32'h0001_0000Expected output
legal: $countones(value) = 1Exactly bit 16 is set, so $countones(value) equals one.
What to cover
Requirements
- Allow every value from 32'h0000_0001 through 32'h8000_0000 that has one set bit.
- Reject zero.
- Reject values with two or more set bits.
- Express the condition as an integral constraint without post_randomize repair.