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Hardware interview practice

Compare One-, Two-, and Three-Process FSM Coding Styles

MediumTimingSystemVerilog

Three engineers code the same fully specified controller as one clocked process, as a state-register process plus combined next-state/output logic, and as separate state-register, next-state, and output processes. Which claim is correct when all three versions implement the same registered behavior?

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Answer choices

  1. A. The three-process version is guaranteed to have the highest clock frequency because more always blocks create more pipeline stages.
  2. B. The one-process version cannot describe a Mealy output under any circumstances.
  3. C. Synthesis can produce equivalent hardware; the process split mainly changes code organization, where defaults are required, and whether output registration is explicit, so each version still needs complete assignments and safe reset handling.
  4. D. The two-process version never needs default assignments because next-state logic is combinational.
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