Hardware interview practice

Code a parameterized 4-to-1 mux two ways

EasyRTL DesignSystemVerilog

Two implementations of one width-parameterized multiplexer must agree for every legal select value. Write behavioral and structural SystemVerilog versions of the 4-to-1 mux.

Starting point

Question code

parameter int W = 8
input logic [W-1:0] d0,d1,d2,d3
input logic [1:0] sel
output logic [W-1:0] y_case
output logic [W-1:0] y_tree

Reviewed example

Work through one case

Input

Case 1: d0,d1,d2,d3 = 8'h10, 8'h20, 8'h30, 8'h40 and sel=0
Case 2: The same data with sel=3
Case 3: sel=2'bx1

Expected output

Case 1: Gives 8'h10.
Case 2: Gives 8'h40.
Case 3: Gives 'x on both outputs.

The shown result follows by applying this rule: Both descriptions implement the same 4-to-1 function. The cases also demonstrate this requirement: Assert y_case === y_tree for all legal select values and all widths W >= 1.

What to cover

Requirements

Implement y_case in always_comb with a complete case over the four legal select values.
Implement y_tree as three explicit 2-to-1 conditional selections.
For a select containing X or Z, drive both outputs to 'x rather than infer storage.
Assert y_case === y_tree for all legal select values and all widths W >= 1.