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Choose directed or constrained-random debug stimulus

EasyDesign VerificationSystemVerilog

A FIFO underflow bug is already known and has a short failing transaction sequence. Which verification approach is strongest?

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Answer choices

  1. A. Use formal equivalence instead of checking the FIFO’s specified behavior.
  2. B. Reproduce it with a short directed test, then add constrained-random tests for nearby interactions.
  3. C. Use code coverage without a checker.
  4. D. Use constrained-random stimulus only and discard the known sequence.
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Reference ModelsMatch transactions in strict order→RTL DesignBuild a synchronous FIFO and race-free BFM→Hardware-Software IntegrationVerify keypad expansion and FIFO draining→
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