Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Build parameterized pack and unpack helpers

Hardware interview practice

Build parameterized pack and unpack helpers

MediumBit ManipulationSystemVerilog

Create reusable helpers that pack N words of W bits into one vector and unpack that vector with word 0 in the least-significant lane.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Reviewed example

Work through one case

Input
N=3, W=4, words[0:2] = [4'hA, 4'h3, 4'hF]
Expected output
packed = 12'hF3A; unpack(packed) = [A, 3, F]

Word zero occupies the least-significant nibble, so the same indexed part-select convention makes pack and unpack exact inverses.

What to cover

Requirements

  1. Support compile-time N and W parameters.
  2. Use one explicit indexed part-select mapping in both directions.
  3. Initialize the packed result before assigning slices.
asic.fyi · Learn silicon end to end.info@asic.fyi