Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Build a deterministic memory-lane error histogram

Hardware interview practice

Build a deterministic memory-lane error histogram

MediumPost-Silicon ValidationC

A lab log contains the lane number for each observed error. Firmware must return all lane counts and the hottest lane. Implement the C histogram helper with transactional outputs.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Starting point

Question code

enum HistStatus { HIST_OK, HIST_BAD_ARG };
HistStatus lane_histogram(const uint8_t *events, size_t n, uint8_t lanes,
uint32_t *counts, uint8_t *hottest);
Reviewed example

Work through one case

Input
events = {2, 1, 2, 3, 1, 2}, lanes = 4.
Expected output
counts = {0, 2, 3, 1} and hottest = 2.

Lane 2 occurs three times, more than every other lane, so it is the unique hottest lane.

What to cover

Requirements

  1. Require lanes in 1..32, counts and hottest nonnull, and events nonnull when n>0; reject n values that could overflow a uint32_t lane count.
  2. Every event must be below lanes. Validate the complete input before changing counts or *hottest.
  3. On success overwrite counts[0..lanes-1] with exact occurrence counts and set hottest to the lane with greatest count.
  4. Break a count tie in favor of the lowest lane number; n=0 therefore returns all-zero counts and hottest=0.
asic.fyi · Learn silicon end to end.info@asic.fyi