Hardware interview practice

Build a 256-bit serial collector reference model

MediumDesign VerificationSystemVerilog

A one-bit stream is MSB-first. Only cycles with in_valid=1 are accepted. There is no input backpressure, and the model emits one word when it accepts bit 256. Build the cycle-accurate reference model.

Starting point

Question code

module serial256_ref(
  input logic clk,rst_n,in_valid,in_bit,
  output logic out_valid, output logic [255:0] out_word
);

Reviewed example

Work through one case

Input

Case 1: Accepting 256 zero bits
Case 2: Accepting one followed by 255 zeros
Case 3: Accepting 255 zeros followed by one at E0

Expected output

Case 1: Produces out_word=256'h0 with one out_valid pulse.
Case 2: Produces out_word=256'h8000000000000000000000000000000000000000000000000000000000000000.
Case 3: Produces out_word=256'h1 with out_valid high immediately after E0; inserted invalid cycles do not move that one's position.

The shown result follows by applying this rule: Maintain a 256-bit shift register and an accepted-bit counter updated only on valid cycles. The cases also demonstrate this requirement: If bit 256 is accepted at rising edge E0, update out_word and assert out_valid immediately after E0 for the E0-to-E1 cycle. At E1, deassert out_valid and allow acceptance of bit 1 of the next word; do not add another pending-result stage.

What to cover

Requirements

An active-low synchronous reset discards a partial word, clears out_word, and forces out_valid low.
Shift exactly one bit on each in_valid cycle; invalid cycles preserve the partial word and accepted-bit count.
The first accepted bit becomes out_word[255] and the 256th becomes out_word[0].
If bit 256 is accepted at rising edge E0, update out_word and assert out_valid immediately after E0 for the E0-to-E1 cycle. At E1, deassert out_valid and allow acceptance of bit 1 of the next word; do not add another pending-result stage.