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Background objections and blocking gets

MediumVerification UtilitiesSystemVerilog

A scoreboard raises a run-phase objection, then forever blocks on analysis_fifo.get. No component can signal an end marker. Why does simulation never leave run_phase?

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Answer choices

  1. A. run_phase ends only after every FIFO reaches its maximum size
  2. B. analysis_fifo.get automatically raises a factory override
  3. C. Scoreboards are forbidden from using task-based TLM calls
  4. D. The scoreboard holds an objection in a loop with no reachable drop, so quiescence elsewhere cannot end the phase
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